Semi-Programmable
New Architectures Optimize the Mix

It stands to reason.

Some components of system-on-chip design are static. You’re not going back and re-engineering them every two weeks. The multiplier was designed long ago and doesn’t really need to be designed again every time the moon changes phase. Neither does the PCI core, for that matter. They’re both stable and well-debugged. It’s unlikely that you’re ever going to need to modify or reconfigure them.

Why, then, does it make sense for these common functions to be built out of programmable logic, subject to the performance, area, and power penalties of LUT-based implementations, and at risk for the random timing and layout problems that can creep into large FPGA designs with soft macros? Of course, it does not.

The major FPGA vendors figured this out some time ago and began putting the very common functions (like multipliers) in hard, cell-based-like implementations on their FPGAs. For a small silicon investment, stable functions could be accelerated to ASIC performance and power, leaving more LUTs for the logic that needed them. This architectural addition makes good sense and has become an accepted feature of most high- (and now even some low-) end FPGAs. [more]

Xilinx Goes Retro
Moving Ahead by Looking Back

All the FPGA action these days is in the new, emerging markets right? As we’ve all discussed for awhile, CPLDs are a nice steady market with slow growth, and networking apps (the ones that built the FPGA industry to where it is today) took a nose-dive a few years back and are out of favor.

According to the world’s largest programmable logic company, this line of reasoning is a bit short-sighted. While Xilinx agrees that there are new and exciting emerging markets out there, they are pointing out, with two announcements this week, that some of the new and exciting opportunities are built right on top of the old, boring ones.

For example, the world is filled with circuit boards that still use old, near obsolete discrete logic components. For the companies that manufacture products that use these boards, there is an enormous opportunity for saving cost, power, and board complexity by consolidating groups of these assorted components into CPLDs. The problem is that the logic designers that created these masterpieces of old are not exactly hanging around waiting for the opportunity to cost-reduce their work from 10 years ago. The people who actually care the most about the problem, the purchasing managers, are generally ill-equipped to make a case for taking action. [more]

Prototype to Production
Structured ASIC Lowers Cost and Power

FPGAs are a great solution for prototyping because they offer designers the flexibility to test a design in the application without incurring large NRE charges. Design iterations can be performed using the same FPGA prototype device until the final working solution is attained. However, a completed design often requires a different set of priorities: lower cost, lower power and better performance. Structured ASICs offer a solution to this shift from a prototype emphasis to production design requirements at less risk than a comparable cell-based ASIC implementation. Structured ASICs also offer several key performance advantages over FPGAs, primarily in the areas of power reduction, clock performance and core density.

Due to their programmable nature, FPGAs use a great deal more power than ASICs. The most advanced FPGAs offer users a reasonable amount of logic and memory, and by default an enormous number of transistors are required to support that capacity. Most designs do not use everything available in the FPGA so a large portion of the transistors are active although not used in the functional circuit. This is a constant source of power drain on the completed design. [more]